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CoreSight™ Definitions

It is useful to have a basic understanding of these terms:

  1. JTAG: Provides access to the CoreSight debugging module located on the Cortex processor. It uses 4 to 5 pins.
  2. Serial Wire Debug (SWD): is a two pin alternative to JTAG and has about the same capabilities except Boundary Scan is not possible. SWD is referenced as SW in the µVision Cortex-M Target Driver Setup. The SWJ box must be selected in ULINK2 or ULINKpro. Serial Wire Viewer (SWV) must use SWD because the JTAG signal TDIO shares the same pin as SWO. The SWV data normally comes from the SWO pin.
  1. Debug Access Port (DAP): This component is accessed via the JTAG or SWD port. One of the features of the DAP are the memory read and write accesses which provide on-the-fly memory accesses without the need for processor core intervention. µVision uses the DAP to update memory, watch and RTOS kernel awareness windows in real-time while the processor is running. You can also modify variable values on the fly. No CPU cycles are used. The program can be running and no source code stubs are needed. You do not need to configure or activate DAP. µVision configures DAP when you select a function that uses it.
  2. Serial Wire Viewer (SWV): A trace capability providing display of reads, writes, exceptions, PC Samples and printf.
  3. Serial Wire Output (SWO): SWV frames usually come out this one pin output. It shares the JTAG signal TDIO.
  4. Instrumentation Trace Macrocell (ITM): As used by µVision, ITM is 32-bit memory addresses (Port 0 through 31) that when written to, will be output on either the SWO or Trace Port. This is useful for printf type operations. µVision uses Port 0 for printf and Port 31 for the RTOS Event Viewer. The data can be saved to a file.
  5. Trace Port: A 4-bit port that ULINKpro uses to collect ETM frames and optionally SWV (rather than through the SWO pin).
  6. Embedded Trace Macrocell (ETM): Displays all the executed instructions. ULINKpro provides ETM trace. ETM requires a special 20-pin Cortex Debug + ETM Connector. ETM also provides Code Coverage and Performance Analysis.
  7. Embedded Trace Buffer (ETB): A small amount of internal RAM used as an ETM trace buffer. This trace does not need a specialized debug adapter such as a ULINKpro. ETB runs as fast as the processor and is especially useful for very fast Cortex processors. ETB is implementation specific.
  8. Micro Trace Buffer (MTB). A portion of the device's internal RAM is used for an instruction trace buffer. Only available on certain Cortex-M0+ processors. Cortex-M3, Cortex-M4 and Cortex-M7 processors usually offer ETM trace to provide Instruction Trace.
  9. Hardware Breakpoints: ARM® Cortex®-M0 and Cortex-M0+ have up to 4 breakpoints. Cortex-M3, Cortex-M4 and Cortex-M7 have up to 6 breakpoints. The final number in a microcontroller device is implementation specific. These can be set/unset on-the-fly without stopping the processor. When a breakpoint is hit, the processor enters Debug state and does not execute the instruction the breakpoint is set on.
  10. Watchpoints: All Cortex-M devices have up to 2 Watchpoints (implementation specific). These are conditional breakpoints. Using watchpoints you can check whether an address has been accessed. Data value matching for watchpoints is only available in certain implementations with a full debug configuration. Check your device's datasheet for details.

Note Note

ARM Cortex-M0 and Cortex-M0+ have only features 1) through 3) plus 9) and 10) implemented. Cortex-M3, Cortex-M4 and Cortex-M7 have all features listed implemented. ETM Instruction trace and trace port are implementation specific. Consult your device's datasheet to determine its feature set.

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